1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device, and more particularly to a method of fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and SOI substrate on the same chip.
2. Description of the Related Art
Using merged dynamic random access memory (DRAM) and logic technology to fabricate a system on a semiconductor chip (e.g., so-called xe2x80x9csystem-on-chipxe2x80x9d (SOC)) has many advantages including reduction of memory latency, larger bandwidth, high-speed processing, and cost reduction.
For deep submicron CMOS logic devices, it is advantageous to build the circuits on silicon on insulator (SOI) substrate to improve the performance. However, due to the buried oxide structure and processing techniques used to form an SOI substrate, many devices cannot be built easily on the SOI substrate. For example, a large capacitor on SOI will have a difficult time making contact to the ground node. As another example, the deep trench capacitor DRAM devices, which are typically built on a bulk silicon substrate, are very difficult to integrate into the SOI substrate, as the merged DRAM/logic technology. That is, the deep trench capacitor DRAM typically cannot be built on the SOI because of the oxide barrier of the SOI which makes trench processing very complicated.
Thus, as the logic technology migrates to silicon-on-insulator (SOI) substrate technology, it becomes difficult to fabricate a DRAM that requires deep trench capacitor structures, or having a large-sized capacitor.
Additionally, thermal dissipation is poor for devices built on the conventional SOI substrate. High temperature will cause great performance degradation.
Moreover, if analog and digital devices are built on a single substrate (e.g., bulk), then high frequency noise (interference) results from the mixed signals. That is, there is no separation of noise-sensitive and noise-insensitive devices and thus the signals output therefrom are subject to interference.
In view of the foregoing and other problems of the conventional methods and structures, an object of the present invention is to provide a method for forming a mixed bulk and SOI structure.
Another object is to provide a method and structure in which complementary metal oxide semiconductor (CMOS) circuit is built strategically on a silicon-on-insulator (SOI) structure and bulk. For example, in an exemplary implementation, a high speed circuit can be built on the SOI substrate, and temperature-sensitive circuits can be fabricated on a bulk substrate. As another example, noise-sensitive circuits can be built on SOI region where the circuits are completely isolated by the oxide including the buried oxide layer, and noise-less or noise-insensitive circuits are built in the bulk structure.
Further, another object is to provide a process for merging silicon-on-insulator and bulk substrate technology on the same substrate so that the DRAM array with deep trench cells is formed on bulk and the logic device(s) is formed on SOI.
In a first aspect of the present invention, a method of forming a semiconductor device, includes patterning a groove into a bulk silicon substrate, forming an oxide in said groove and planarizing the silicon substrate to form at least one patterned oxide island in the silicon substrate, forming a silicon layer on exposed portions of the silicon substrate and the at least one oxide island, crystallizing the silicon layer using the exposed silicon substrate as a seed, the silicon substrate having direct contact with the formed silicon layer serving as a crystal growth seeding for the crystallization process, and converting the silicon layer to crystallized silicon, performing a shallow trench isolation (STI) process for device isolation as well as for removing defective regions after silicon crystallization to form the oxide isolations between devices, wherein a portion of the silicon layer above the islands is etched to form a cavity and then the same material as the islands is deposited in the cavity, and planarizing the upper surface to complete the oxide isolations. It is noted that an advantage of the present invention is that by performing the STI process also simultaneously removes the defective regions by filling the same with oxide.
In another aspect of the invention, a semiconductor device formed by the above method is provided.
Thus, according to the present invention, a method and structure are provided which produce a patterned SOI substrate where DRAM devices can be built on the bulk substrate while the logic devices (as well as the peripheral devices for the DRAM devices) are built on the patterned SOI substrate.
With the unique and unobvious features of the invention, memory circuits, for example, dynamic random access memory (DRAM) and logic technology, can be efficiently merged to fabricate an entire system on a semiconductor chip such that memory latency is reduced, bandwidth is increased, and high-speed processing and cost reduction result.
The present invention is also advantageous, for example, from a process point of view. Specifically, as compared to the conventional patterned SIMOX technique, which results in a much higher number of defect counts per unit area (or defect density), the method of the present invention results in a much better substrate quality. This higher substrate quality is because the stress from lattice mismatch (e.g., of the oxide and the silicon) is more by high energy oxygen implantation. The defective regions resulting from the method of the present invention are also predictable and therefore can be completely removed in a subsequent shallow trench formation.